In recent years, along with the high integration and high performance of a semiconductor integrated circuit (LSI), micron order fine processing technologies have been proposed. In particular, recently, in order to achieve high-speed LSI, a wiring material is being changed from conventional aluminum (Al) alloy to low resistance copper (Cu) or Cu alloy (hereinafter, collectively referred to as Cu).
In a wiring process of the semiconductor manufacture, a wiring pattern is formed by using, e.g., photolithography and reactive ion etching (RIE). On an insulating film on which the wiring pattern has been formed, a barrier metal layer and a Cu seed layer are formed mainly by physical vapor deposition (PVD). Then, Cu is embedded in the wiring pattern by an electrolytic plating method and a Cu film other than a portion embedded in a groove is removed by chemical mechanical polishing, thereby forming a wiring layer (see, e.g., Japanese Patent Application Publication No. 2007-317702).
The wiring forming method is referred to as a damascene method. In case of forming multilayer Cu wiring, in particular, a wiring forming method called a dual damascene structure is also used. In this method, an insulating film is deposited on the lower wiring, and after forming a predetermined via hole and a trench for the upper wiring, Cu serving as a wiring material is embedded in the via hole and the trench. Further, the wiring layer is formed by performing planarization to remove unnecessary Cu of the upper layer by chemical mechanical polishing.
A low-k film (low dielectric constant material film) may be used as the interlayer insulating film. Accordingly, by using a low-k film with a dielectric constant lower than that of a silicon oxide film, it is possible to reduce the parasitic capacitance between wires. When forming Cu wiring, a barrier metal film is formed between Cu and the low-k film in order to prevent Cu from diffusing into the low-k film.
In this case, in order to embed Cu in the via hole or trench by an electrolytic plating method, it requires a seed film serving as a cathode. However, if a via hole diameter or trench width becomes narrower with high integration, there may occur a region where a Cu seed film is not formed especially in the vicinity of the bottom of the groove. Consequently, in this region, Cu is not plated, which may cause embedding defects.